The sample/hold circuit is used to stabilize the input signal during the comparison by the flash converter in the digitizer. The digitizer can operate without a S/H, due to the limited number of levels, but some harmonic distortion or bandpass effects may occur in real life due to the close spacing of the levels in a 3-bit converter. The S/H is therefore a backup option, to insure that the sampler will operate correctly even with 3-bit quantization.
The S/H circuit requires a 4 GHz sinusoidal clock (0 dBm nominal), and has an internal clipping circuit to protect the input from signal spikes. Both input and output buffers are matched at 50 ohm, and operate at signal level around 0 dBm. At 4 GHz clock, the input window is less than 50 ps, and the stable output is from 80 to 180 ps referred to the clock rising edge.
The sampled signal stream, at 4 GS/s, must be parallelized to several parallel streams at lower speed in order to be processed by standard logic. The fiber optic formatter accepts 16 streams at 250 MS/s, syncronized to the system 125 MHz clock.
No commercial demultiplexers are avaliable using an external low frequency clock for frame syncronization. A custom chip has therefore to be designed.
Two solutions have been proposed for the demultiplexer, both operating separately on each data bit. A direct 1:16 SiGe is currently being developed by the Grenoble group. In Arcetri, a 1:8 GaAs chip, using SBCL logic, has been designed, followed by a 1:2 demux implemented in a FPGA.
The chip requires two sinusoidal clocks, at 4 and 0.5 GHz. The FPGA generates internally the 250 MHz clock from an external reference.
The chip is sized 2x3 mm. It is physically mounted on a high Er substrate chip, sized 10x12 mm, with coplanar lines to bring the signals to the SMD pads.
Work in Arcetri: